Intel Patent Outlines XBM Architecture to Replace HBM Interposers

A patent application published on July 2, 2026, outlines an Intel concept for an alternative memory architecture dubbed Cross-Batch Memory (XBM). According to reports by Tom's Hardware and Wccftech based on the filing, the design aims to match the footprint and bandwidth targets of future HBM4 stacks while eliminating the dedicated silicon interposer that currently constrains high-end accelerator packaging.

Conventional High Bandwidth Memory (HBM) relies on a massive parallel bus—typically 1,024 bits or wider—routed through an interposer between stacked DRAM dies and a host processor. That requirement links production directly to specialized, capacity-constrained packaging lines such as TSMC's CoWoS. Intel's proposed alternative shifts data transfers to standard UCIe (Universal Chiplet Interconnect Express) links running at 32 GT/s through a base die.

Under the filing's specifications, Intel details memory dies configured with 768 data blocks arranged in a 32-by-24 grid, partitioned into eight channels with eight sub-channels each. The architecture envisions vertical stacks scaling from 8 to 16 tiers, offering per-die capacities between 0.5 GB and 5.0 GB. Channels are described as operating at 2 GHz, with support for configurations like Memory-on-Package (MoP) to reduce package z-height by up to 350 microns via techniques like reversed overhang.

Beyond interconnects, the patent proposes shifting memory cell fabrication. Instead of traditional Front-End-of-Line (FEOL) silicon substrates, Intel suggests forming 1T1C cells during Back-End-of-Line (BEOL) metallization stages using thin-film transistors. To manage yield penalties inherent to dense vertical manufacturing, the base die integrates Built-In Self-Repair (BISR) logic alongside dedicated redundant channels and spare memory sub-channels to substitute flawed cells dynamically.

The concept remains strictly a patent filing without a commercial release target or roadmap. Intel is simultaneously exploring Z-Angle Memory (ZAM) alongside a partner with an eye on 2029, whereas UCIe link limits and unproven high-volume manufacturing of BEOL DRAM mean Intel's interposer-free design remains an unproven theoretical hedge.

Source: habr